PIC18F8585T-I/PT【PDF 260/424 页】IC PIC MCU FLASH 24KX16 80TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3881

256页 257页 258页 259页 [260页]261页 262页 263页 264页

PIC18F6585/8585/6680/8680

DS30491C-page 330

2004 Microchip Technology Inc.

When a receive buffer is programmed to use standard

identifier messages, part of the full Acceptance Filter

data byte filter is programmable from 0 to 18 bits. This

functionality simplifies implementation of high-level

protocols, such as DeviceNet.

The following is the list of resources available in Mode 1:

Three transmit buffers: TXB0, TXB1 and TXB2

Two receive buffers: RXB0 and RXB1

Six buffers programmable as TX or RX: B0-B5

Automatic RTR handling on B0-B5

Sixteen dynamically assigned acceptance filters:

RXF0-RXF15

Two dedicated Acceptance Mask registers;

RXF15 programmable as third mask:

RXM0-RXM1, RXF15

Programmable data filter on standard identifier

messages: SDFLC

23.4.3

MODE 2 – ENHANCED FIFO MODE

In Mode 2, two or more receive buffers are used to form

the receive FIFO (First In First Out) buffer. There is no

one-to-one relation between the receive buffer and

Acceptance Filter registers. Any filter that is enabled

and linked to any FIFO receive buffer can generate

acceptance and cause FIFO to be updated.

FIFO length is user programmable, from 2-8 buffers

deep. FIFO length is determined by the very first

programmable buffer that is configured as a transmit

buffer. For example, if Buffer 2 (B2) is programmed as

a transmit buffer, FIFO consists of RXB0, RXB1, B0

and B1 – creating a FIFO length of 4. If all programma-

ble buffers are configured as receive buffers, FIFO will

have the maximum length of 8.

The following is the list of resources available in Mode 2:

Three transmit buffers: TXB0, TXB1 and TXB2

Two receive buffers: RXB0 and RXB1

Six buffers programmable as TX or RX; receive

buffers form FIFO: B0-B5

Automatic RTR handling on B0-B5

Sixteen acceptance filters: RXF0-RXF15

Two dedicated Acceptance Mask registers;

RXF15 programmable as third mask:

RXM0-RXM1, RXF15

Programmable data filter on standard identifier

messages: SDFLC, useful for DeviceNet protocol

23.5

CAN Message Buffers

23.5.1

DEDICATED TRANSMIT BUFFERS

The PIC18F6585/8585/6680/8680 devices implement

three dedicated transmit buffers – TXB0, TXB1 and

TXB2. Each of these buffers occupies 14 bytes of

SRAM and are mapped into the SFR memory map.

These are the only transmit buffers available in

Mode 0. Mode 1 and 2 may access these and other

additional buffers.

Each transmit buffer contains one Control register

(TXBnCON), four Identifier registers (TXBnSIDL,

TXBnSIDH, TXBnEIDL, TXBnEIDH), one Data Length

Count register (TXBnDLC) and eight Data Byte

registers (TXBnDm).

23.5.2

DEDICATED RECEIVE BUFFERS

The PIC18F6585/8585/6680/8680 devices implement

two dedicated receive buffers – RXB0 and RXB1. Each

of these buffers occupies 14 bytes of SRAM and are

mapped into SFR memory map. These are the only

receive buffers available in Mode 0. Mode 1 and 2 may

access these and other additional buffers.

Each receive buffer contains one Control register

(RXBnCON), four Identifier registers (RXBnSIDL,

RXBnSIDH, RXBnEIDL, RXBnEIDH), one Data Length

Count register (RXBnDLC) and eight Data Byte

registers (RXBnDm).

There is also a separate Message Assembly Buffer

(MAB) which acts as an additional receive buffer. MAB

is always committed to receiving the next message

from the bus and is not directly accessible to user firm-

ware. The MAB assembles all incoming messages one

by one. A message is transferred to appropriate

receive buffers only if the corresponding acceptance

filter criteria is met.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式